1. Field of the Invention
The present invention relates to transistor structures, to memory structures and to methods of operating the same.
2. Description of Related Art
In integrated circuit design, it is desirable to utilize transistors that have fast transitions between on and off states, and low leakage current. One parameter associated with transition time and leakage current for CMOS transistors is known as subthreshold slope, which is often characterized in millivolts of gate voltage per decade of drain current, where a “decade” corresponds to a 10 times increase in drain current. It is believed that the subthreshold slope for CMOS transistors cannot be better than about 60 mV/decade at room temperature.
In the CMOS designs, transistors are included that are configured for n-channel mode (when the channel is on, electrons are charge carriers), and other transistors are included that are configured for p-channel mode (when the channel is on, holes are charge carriers). The n-channel or p-channel mode is set by the structure of the transistor. This can limit flexibility in the layout of an integrated circuit, and in the implementation of circuitry utilizing the transistors.
Thus it is desirable to provide transistor structures that address limitations of prior designs.
Leakage current and transition times are also important parameters in the design of high density memory. Also, in charge trapping memory cells based on MOS transistor-like structures, it can be necessary to provide both types of charge carrier in the channel of a memory cell for the purposes of program or erase operations.
Further limitations in many types of prior art flash memory technologies relate to the requirement for block erase operations. Because of the reliance on block erase, the complexity of the required operations and the amount of required time for writing data in random addresses of the flash memory are increased.
It is desirable therefore, in addition, to provide memory structures that support more efficient operation and low leakage.